MOSFETs and catch diodes

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Introduction

In the previous set of articles I’ve gone to excruciating details of each of the drive modes: the sign-magnitude drive, the lock anti-phase drive and the asynchronous sign-magnitude drive. To recap, the most important equations and properties of each of the drive modes are in the table below:

Sign-magnitude drive Lock anti-phase drive Async. Sign-magnitude drive
Average motor current (Imot_avg) (Vmot_avg-Vg)/Rm (Vmot_avg-Vg)/Rm (Vavg_conduct – Vg) / Rm
Average motor voltage (Vmot_avg) Vbat * ton/tcycle Vbat*(ton-toff)/tcycle (Vbat*ton + Vg*toff_zero)/tcycle
Maximum ripple current (Iripple_max) Vbat / Lm * tcycle/4 1/2*Vbat/L*tcycle Vbat / Lm * tcycle/4
Input capacitor (Cinput) 1/64 * Vbat/Vmax_bat_ripple / Lm * tcycle2 1/2 * Imot_avg / Vbat_ripple * tcycle Lm/Rm * (Imax + (Vbat/Rm) * ln(1 + Imax / (Vbat/Rm + Imax) ) / Vripple_max
Regenerative braking Yes Yes No
Dynamic braking Yes Yes Yes

As usual, I include the bridge circuit schematic:

and our motor model as well as a reminder:

With all that math and theory behind us, we can come back to practical questions of how to go about actually designing an H-bridge. In this article I will go though the high level design decisions to make and the major component selection questions. I will leave some of the intricacies and the drive-circuit design for a later installment.

High level design parameters

The design of an H-bridge usually starts with making some high-level decisions. These are:

  1. The maximum operating voltage (Vbat) of the bridge
  2. The maximum (average) motor current that the bridge needs to handle
  3. The drive mode of the bridge
  4. The switching frequency of the bridge

The first two questions are relatively easy to answer when you have a particular application or motor to drive. The drive mode is a complex problem, but the above table should give you a rough idea of the major trade-offs between the options. We will come back to the nuances of the drive mode options when we talk about drive circuits. The switching frequency selection we haven’t talked so much about yet so lets spend some time on it. There are several things to consider:

  • If the switching cycle time (tcycle, the inverse of the switching frequency) is not quite a bit smaller then the electrical time-constant of the motor (Lm/Rm), the on-time and off-time current changes are no longer linear. This invalidates most of the calculations above in the table and in the previous articles so if you choose such a low frequency you’re pretty much on your own. At the same time I see no reason to run at such a low frequency and I hope you won’t either after reading through the rest of the items.
  • The other factor to consider is that the ripple current (Iripple_max) is directly proportional to tcycle. So as your operating frequency increases, the ripple current decreases. Usually you want as low of a ripple current as possible because it stresses components, reduces efficiency (additional loss on various resistances on wires, connectors, switching elements etc.) and generates EMI noise.
  • In some drive-modes the size of the required input capacitor depends on the operating frequency. The higher it is, the lower the input capacitance needs to be.
  • The switching of the voltage generates an audible ‘buzz’ on the motor. To avoid this buzz you have to go up to ultrasonic ranges, basically above 20kHz. Of course if audible noise is not a concern in your application than this consideration doesn’t apply to you.
  • As we will discuss it later, the higher the switching frequency is, the higher the switching losses on the bridge are, and at some point they start to be a significant source of heat. This will limit your ability to increase the switching frequency arbitrarily high.
  • As the switching frequency increases, you will want to turn the switching elements on- and off- faster to minimize the above mentioned switching loss. That makes the drive-circuit design harder as well as make the circuit more ‘noisy’, emitting more EMI radiation.

Overall, today it seems that 20-40kHz switching frequency is a good compromise between these requirements for most designs. This is somewhat of a moving target however as component technology improves and of course depends on the application as well.

Component selection

Once you more or less have decided on the above design parameters, you can start looking for components. In a bridge, there are eight components of interest: the four switching elements and the four catch diodes. You of course will have to design the drive circuit as well that involves further component selection, but I’ll discuss those issues later.

Switching elements – MOSFETs

One of the key decision to make for an H-bridge is the selection of the switching elements. There are many factors to be considered, the most important ones are the operating current, the operating voltage and the switching frequency. For really high-voltage applications (several hundred volts) IGBTs are becoming popular and there are still some bridges out there using BJTs, however the vast majority of the modern designs use MOSFETs, so for the rest of the document I will assume MOSFET switching elements.

MOSFETs, when operated as switches, have two states: on and off. In the ‘on’ state they more or less behave like a small resistor, and their resistance is denoted by rdson. Obviously the higher this value is, the higher the losses are on the MOSFET. While efficiency is not a big concern for most H-bridge designs, heat is. Since the loss on the MOSFET is converted to heat that has to be dissipated, the lower rdson is the better. Another factor to consider is that rdson is temperature-dependent and increases with temperature. Datasheets usually brag about rdson at 25oC, but that hardly can be considered as normal operating condition. So always look for rdson over the full temperature range to make sure you’re operating within safe limits.

P- VERSUS N-CHANNEL

Right after deciding on MOSFET technology to use, the next question to answer is to use ‘N’-channel or ‘P’-channel MOSFETs. ‘N’ channel MOSFETs have a much lower rdson so it would appear, that N-channel devices are desirable for their lower losses. For the low-side switches (Q2 and Q4) they are the obvious choice in deed. For the high-side switches (Q1 and Q3) the picture however is more complicated.

For N-channel devices to work, their drain needs to be at a higher potential than their source (otherwise their body-diode would open). So, when operated on the high-side, their source is connected to the motor terminal, and their drain is to the power supply:

image

This means that their source terminal potential can be anywhere between ground and Vbat. In order to turn the FET properly on, their gate should be (depending on construction) 3-12V higher than their source. At the same time, MOSFETs are very sensitive to the maximum gate-sources voltage allowed on them. This is specified in the datasheet, but normally you will destroy your FET if you ever put more than 20V or so between its gate and source. This means that in order to properly and safely turn on a high-side N-MOSFET you need a varying gate-voltage that is potentially higher than Vbat. We’ll come back to this later, for now it suffice to say, that this requirement complicates driver design quite a bit.

P-channel devices don’t have this problem: their source is connected to Vbat, while their drain is on the motor terminal.

image

They need a negative 3-12V on their gate compared to their source to turn them on, so the the gate voltage is clearly always below Vbat and can be kept within safe limits without monitoring the motor terminal voltage. Not only P-channel devices usually have a higher rdson, they are also slower to turn on and off. This will aggravate dynamic loss problems. and potentially complicate shoot-through protection.

Overall the usual trade-off is that for undemanding applications P-MOSFETs are selected for high-side operation as rdson is not going to be a big problem, losses are manageable and they require much simpler drive circuitry. For high-current applications N-channel devices are a better compromise as P-FETs with comparable rdson are either not available or extremely expensive making it reasonable to spend some extra money on the drive circuit.

Package selection and thermal management

Once you settle on the channel-type you can start looking at device datasheets. The goal is to arrive at is the maximum allowed rdson for the device. It will depend on the maximum average motor current and the available cooling. Because MOSFETs – when they’re on –can be basically though of as resistors, the dissipated heat on them is going to be:

P = rdson * Iavg2

Now, the average current used here is the average current through the FET, not necessarily through the motor, but in most applications it’s a good conservative approach to use the maximum allowed (average) motor current for this exercise. From this, the on-resistance for the FETs need to be:

rdson < Pmax/Imot_avg_max2

If you want to figure out how much power a FET can dissipate, you have to start by looking at its packaging. As a guideline, the bigger the package is, the more heat it can dissipate. Common packages include SO-8, D-PAQ and D2-PAQ for surface mount and TO-92, TO-220 and TO-3 for through-hole mounting. There are of course other exotic packages and new ones are introduced almost every day.

The main characteristics that you’re looking for is the ‘thermal resistance’ of the package, usually denoted as RΘ. The way to use it is this: the temperature difference between the two ‘things’ the thermal resistance is measured between will be ΔT = RΘ*P, where P is the dissipated power transferred between the two ‘things’.

The datasheets also specify how hot the chip (or die) can become before it gets damaged.

The most valuable parameter consequently is the junction-to-ambient thermal resistance, that tells you how much hotter the chip is than the air that surrounds the package. There are some complications in determining that number as it depends on a lot of design-parameters so in many cases the datasheet will only contain another parameter, the junction-to-case thermal resistance. That tells you how much hotter the chip inside the package is than the outside of the case at a certain power dissipation but it leaves it up to you to figure out how hot the case can become.

When working with surface-mount packages, it is important to note that thermal characteristics are highly dependent on the actual PCB layout. Take the traditional SO-8 package as an example (one typical FET datasheet is here for the FDS8447) You’ll see that with just the minimum amount of copper on the board the package has ~125oC/W thermal resistance. With a 6.5cm2 (1in2) copper area, the same number is less then half of this, ~50oC/W. Let’s say now that the device itself can operate up to 150oC (this is called the maximum allowed junction temperature). If you can keep the surrounding temperature (called ambient temperature) below 50oC, you can can dissipate somewhere between 0.8W ((150-50)/125) and 2W ((150-50)/50) of power on the FET depending on your PCB layout.

Through-hole packages of course also perform very differently with or without heat-sinks. A TO-220 package for example has a ~60oC/W thermal resistance without a heat-sink (here’s a typical TO-220 packaged FET datasheet, the FDP55N06). With the same temperature limits as before, this device can dissipate 1.67W of power. With a heat-sink, like this: http://www.aavidthermalloy.com/products/standard/7023b-mtg you will easily be able to dissipate 9 watts.

Once you figure out how much power you can dissipate on each FET, you can calculate the minimum allowed rdson. As an example, taking the 1.67W power dissipation limit and assuming you want to be able to work with an average 10A of current over the transistor, you get a maximum rdson of 16.7mΩ. That happens to be a quite nice fit for the IRF1010Z MOSFET, which has an rdson of 7.5mΩ at 25oC, and about twice of that at 150oC. Of course if you can provide better cooling with a heat-sink, or a fan (or both) than you can handle much higher average currents, but it is a loosing game: if you can dissipate let’s say four times as much power (6.4W), you can only handle twice the current (20A) with the same rdson.

Turn-on and -off times

If you look at the previous power dissipation equation, you’ll see that lowering rdson is a more promising approach to increasing the current-delivery capability of the bridge without blowing your heat-budget: for example if you want to deliver twice the current you only need to cut rdson in half. There’s a catch though: the lower rdson gets, the bigger the MOSFET becomes. The bigger the physical device is, the bigger it’s gate will be. The gate forms a capacitor towards the source and the drain. Since MOSFETs are voltage driven devices, their gate-source voltage has to be in a certain range (usually above 5-10V) to be fully turned on, and in another range (less than a volt or so) to be turned off. So, the on and off transient has to charge and discharge these parasitic capacitors. If you have only limited current available to drive the gate (and you always do), the higher the gate-capacitance is, the longer it takes to charge or discharge it. Why is it important?

MOSFETs have a low rdson when they are fully on, and they conduct almost no current when they’re are completely off. In both cases the dissipated power is relatively low. However when they transition between these two states, there will be a short period where rdson is relatively high, but not high enough to stop significant current from flowing through the device. In these transitional periods both the voltage drop on the device (due to rdson) and the current through it are significant, resulting in high power-dissipation. Naturally you would like to keep this transition time as low as possible from this perspective (we’ll talk later about reasons why you don’t want it to be too fast either), so a higher gate-capacitance will not be desirable. With a given gate-drive strength the gate capacitance limits the speed by which the element can be turned on and off, and thus poses an operating frequency limit.

With that said, switching loss is usually not that big of an issue in a modern bridge for operating frequencies below let’s say 40kHz, but becomes significant as frequency increases. After a certain point it is the main contributor to the dissipated heat.

Catch diodes

Catch diodes (D1..D4) are often overlooked or just briefly mentioned in most H-bridge descriptions. If you read the introductory article, you’ll understand why: in the two most common drive modes they almost never conduct current for any significant amount of time, and their only purpose is to provide a path for the current to flow in the short transitions between the on-time and the off-time.

In the asynchronous drive mode however, the off-time current flows through the catch diode(s), so – especially for that mode – we’ll have to pay more attention to these components. Whenever a diode is conducting current, there will be a relatively constant voltage drop on it. This is called forward voltage drop and denoted as VF. It is in the 500..1000mV range for most components. This voltage drop, combined with the current through the diode will produce some heat dissipation. The actual heat dissipation depends on the average current flowing through the diode and the percentage of the time the diode is open. The average motor current on the diode is the following (we’re only talking about the asynchronous sign-magnitude drive mode here):

Imot_avg = (Vavg_conduct – Vg) / Rm

and it flows through one of the diodes for toff_conduct amount of time, so the dissipated power is:

Pdiode = (Vavg_conduct – Vg) / Rm * VF * (toff_conduct/tcycle)

Now, when the average current is high, the bridge is in continuous current mode, so we can simplify these equations a little bit, and get:

Pdiode = (Vbat * ton/tcycle – Vg)/Rm * VF * (tcycle – ton)/tcycle

This is a quadratic equation over ton, and reaches its maximum when ton = tcycle/2. Finally, since we don’t know Vg, the generator voltage, the conservative approach to take is to assume Vg to be 0. (In fact the absolute most conservative is to assume Vg is –Vbat, but that’s a really extreme condition. I will stay with Vg = 0 for now, but you can do the math for the other case if you’re extra cautious) With that we get:

Pdiode = 1/4 * Vbat*VF/Rm

As an example, if we assume Rm is 1Ω, Vbat is 20V and VF is only 500mV, we get 2.5W heat dissipated on the diode. You can see that the heat dissipation on the diode (again only for asynchronous sign-magnitude drive) can be significantly higher than that on the MOSFETs.

One important feature of MOSFET transistors is that they contain an intrinsic (unavoidable, built-in) diode between their drain and source. This diode acts as a catch diode in an H-bridge configuration, and most MOSFET datasheets specify the parameters of this diode. In many bridge designs it is possible to use this built-in diode of the transistors and not provide external ones, but the specification of this diode needs to meet the design requirements obviously. For bipolar transistors there’s no such intrinsic diode so external diodes always have to be provided.

If you decide to use external diodes with MOSFETs, make sure that those diodes have a VF lower than that of the body-diodes of the transistors. Otherwise, the diodes inside the FETs will open first and will divert the current from your external diodes.

A nice advantage of using the internal diodes is that – being on the same die, inside the same package – the cooling and heat-sinks that you provide for the FETs will automatically work for the diodes as well. Of course you have to make sure that the cooling is in fact adequate for the diodes, not just the FETs but in many cases this approach results in a simper mechanical construction.

Diodes – mostly when they’re off – have a small capacitance between their leads. This capacitance will have to be discharged before the device can turn on and leads to a delay in response to a sudden change in the voltage. This capacitance depends on many factors, but in general grows with the surface area of the P-N transition, that is the current carrying capability of the device. In short, the beefier the device, the slower it is. When the bridge turns off, the motor current will need a way to continue flowing. The motor will forward-bias a diode (or diodes) in the bridge to create a route for that current, however the turn-on delay of the diodes will create a problem. Without mitigation the motor voltage can rise to dangerous levels and damage the FETs. To bridge this interval where neither the switches nor the diodes conduct a capacitor has to be connected to the terminals of the motor:

image

Some motors contain this capacitor already – they are needed for other reasons as well –  but many require an external one. This capacitor will conduct the current until the diodes open, but the terminal voltage of the motor will still rapidly increase. It is important to select diodes with a short turn-on delay, and this is the reason that Schottky-type diodes are preferred in this role.

Where to go from here

In this article we’ve went through the high-level design decisions that need to be made for an H-Bridge design and the various concerns we have to deal with when selecting the major components: the switching elements and the catch diodes. With that foundation, in the next installment of the series we can go though the various drive circuit options, that is, how to generate the gate voltages for the MOSFETs in the various drive modes.

18 thoughts on “MOSFETs and catch diodes

  1. Hi Andras,
    You have done a fantastic job on these pages, congratulations, my hat’s to you :)!
    I’ve been developing an h-bridge for some time to help out on a friend’s project, and choose to use P-MOSFETs for the top drive. Due to PCB error on a top P driver I had to examine it’s working carefully, and I noticed an “interesting” effect: since the PMOS drain and gate are capacitively coupled, when the bottom same half-bridge (N)MOS turns on, it can be bring the PMOS gate down a bit and even cause it to turn on for a tiny amount of time, generating a small shoot through event. Although it was shorter than 2 – 3us, this caused a huge heating on the PMOS. I’ve studied this also in simulation and it can be seen there too.
    After fixing the top driver the PMOS heating went away, but I can still see the gate going down when the bottom MOSFET turns ON, although it is now for such a short time and by less than 2V that it doesn’t seem to cause any noticeable bad effect anymore. The switching time on the NMOS is short, some 200 – 250ns.
    This effect depends obviously on the strength of the drivers. I’ve designed them with discrete components (I like to design discreet; the schematics is more or less this: http://img853.imageshack.us/img853/7915/halfbridge.png) and never tried chip drivers designed for the task.
    Have you ever ran across this effect? In an all NMOS bridge this shouldn’t be a problem, since the effect will just re-inforce the top NMOS turn off.
    Ehh, sorry for my very long comment!
    Thank you and best regards

    • Nuno,

      Thanks for bringing this effect to my attention. Your analysis is spot on and while I have not seen this problem in my circuits, I’ve done some quick simulations and in fact I’ve seen the effect you describe. I can see how this could easily be a problem. I can think of two simple ways to combat this phenomena:
      1. Increase the drive-strength of your driver. This lowers the cut-off frequency of the R/C filter that the noise needs to travel through, reducing it’s high-frequency content. It unfortunately has the side-effect of making the turn-on and -off-times shorter, which can cause all sorts of problems.
      2. Add a capacitor between the gate and the source of the high-side FET: this effectively creates a capacitive divider for your noise and decrease the spikes on the gate. The negative of this approach is that it makes the turn-on and -off-times longer which is not necessarily a good idea either.

      Probably the best approach is to combine the two: add a capacitor and increase the drive-strength at the same time. This way you can reduce the spikes quite effectively while you retain control over your turn-on and -off-times.

      Regards,
      Andras Tantos

      • I have a few suggestions as well for this issue.

        (1) Increase R24 – Since the parasitic gate-drain capacitor draws current from Vcc, increasing R24 would increase the RC constant.
        (2) Add a resistor in series with the gate – same reasoning as above.
        (3) If you haven’t yet you should add a flyback (or catch) diode. I advise against relying on the FET’s internal one.

        ***(1) and (2) may reduce your turn-on/off time

          • I’m not sure how increasing R24 or adding a series gate-resistor (do you mean increasing R10?) would help here. Both of those approaches would make it easier for the capacitor to drag the gate to whatever voltage it wants to, which is the problem to begin with. In other words, you want to provide a low-resistance path to discharge the parasitic capacitor quickly, so in fact you want to decrease the R/C constant.

            To put it in yet another way: your problem is that at high frequencies, you have a low-impedance path from the drain to the gate on the high-side, allowing noise to couple in. This noise source gets loaded by the impedance of your signal source (gate drive mostly). Your goal is to increase this loading, consequently to reduce the drive impedance.

            Which leads to another approach to combat the problem: add a capacitor in parallel with your gate drive resistor: this way you will decrease only your high-frequency drive impedance. This still has an impact on the turn-on time (it will decrease it) but the change will be less dramatic than if you simply reduced the drive resistor value.

            And yes, I misspoke in my previous reply: you in fact want to decrease the time-constant of your R/C circuit. Sorry about that.

  2. I wired up a bridge to run a thermoelectric element, using the ADP3120A to drive the N-mosfets, and I’m also seeing weird correlated features in the high- and low-side gate voltages similar to what Nuno reported. I thought it was related to the very noisy power supply I’m using, but maybe it also has something to do with this capacitive coupling. In my case I think what happens is that the ADP3102A shoot-through protection circuit, which monitors the gate voltages of the MOSFETS, triggers off of the the low-side gate voltage getting pulled up when the high-side gate goes high. The only thing I can think of is to try to add a bigger bypass capacitor to the APD3102A supply pin.

    • Thanks for your comment.

      I think you’re right that capacitive coupling might play a role in what you see. If I understand you right, you in fact only have a half-bridge circuit, driving a heating element (essentially an inductor in series with a resistor) that is grounded on the other side. You drive the half-bridge in a push-pull fashion, so this setup would correspond to synchronous sign-magnitude drive of an H-bridge with low-side off-time conduction.

      What happens than, is during the off-time the low-side FET is on and the current is circulating through that and the load towards GND. When it comes time to turn the high-side on, you first turn the low-side off to prevent shoot-through. At that point the low-side body-diode takes conduction over and lowers the switching node voltage to ~-0.7V. Now, when you turn the high-side on, the FET needs to lift the switching node from this -0.7V to VCC. This transient will couple to the gate of the low-side FET though the drain-gate capacitance and momentarily turn it on. This transient in fact can confuse the dynamic shoot-through protection in the ADP3120A.

      A very simple experiment to see if this is right is to connect the other end of the heater to VCC instead of GND. That way, the current during shoot-through protection block-out will flow through the high-side body-diode, so by the time the high-side FET would turn on, the switching node would have already be lifted up to around VCC. The reverse situation (when we switch from high- to low-side) should not be a problem as at that point the capacitive coupling on the high-side will maintain the 0V voltage difference between the source and the gate, effectively keeping the high-side FET shut.

      If this experiment shows good results, I would consider the techniques I recommended in the reply to Nuno. I can see that your driver has a very low output resistance, so your output transients must be very fast, unless you add a series resistor to the gates. With the added resistors you can also add parallel capacitors to shunt out the capacitive coupling effect and control both the turn-on and –off time as well as this unfortunate side-effect of the parasitic capacitors at the cost of slightly higher driver power.

      Thanks,
      Andras Tantos

  3. The capacitor in parallel with the gate resistor seems like a good solution, I’ll try it out thanks.

    For the record, this is an oscilloscope trace of the event in the PMOS gate (yellow trace) as it is now (no harm being done):
    http://img41.imageshack.us/img41/3777/pmosgateafterdriverfix.png
    This is the one that made my PMOS burning hot (due to problem in driver):
    http://img137.imageshack.us/img137/420/pmosgatebeforedriverfix.png
    Noe the voltage and time scales.

  4. With regards to the odd transitions experienced. I have suffered on a supplied MCU and I finally tracked it down to the pair of complementary driver emitter follower transistors being effectively open circuit during there cross over point giving the lower FET’s a high (relatively ) impedance during this time on each cycle. Curing this stopped the almost weekly demise of the Motor Control unit especially as the manufacture had accused us of exceeding the dissipation of the 5 (FIVE) failed units returned to him!!

  5. Not exactly on the odd transition experience but also on the “keep em’ quiet when not driven” area :), I had a design fail on my low side discreet BJT driver worth mentioning. It’s this schematic here:
    http://img853.imageshack.us/img853/7915/halfbridge.png
    I added anti-saturation diode (D3 on the bottom left; I actually have schottkys now) to the input transistor, to remove the huge latency when trying to remove the BJT from saturation. Well, at 1st I didn’t notice that the diode would provide a current path through R8 (the “keep the driver off if not driven” resistor :) ) and the zener to GND and therefore put 12V at the output push-pull driver – effectively turning ON the FETs when the driver is not driven :\
    I ended up just removing R8, since the top drivers are OFF if not driven and so no short-circuit will happen when the drivers are not being driven and that is enough for the application. It works, but reliability is definitely not top notch!

  6. Hello I a having a problem of heating in my sine wave inverter I a using irf260n but when I put load on the inverter my fets run real hot . i am using pwm on the gates to produce a sine wave inverter . Could u give me some pointers to help here with this problem.

    • You didn’t give enough information to really help you, but in general, if a FET get’s hot, that’s because it dissipates a lot of power. P = I2R, so it’s either conducting a lot of current, or it has a high gate-resistance. The former can be caused by a number of reasons:

      • Shoot through
      • Short circuit
      • High load current

      The high channel resistance can be because you don’t open the FET fully (too low gate-voltage for example) or don’t close it all the way when it’s off.

      The other possibility is that the catch diode inside the FET conducts too much current or for too extended of a period and that causes heat issues. This can be solved by adjusting the shoot-through protection window or the drive-mode of the bridge.

      Andras Tantos

  7. I really apreciate ur support on the topic Sir. I am using sg3524 to produce the square wave and another ic producing the pwm at 25khz driving through a totem driver to drive 10 irfp 260 n in a pushpull configuration. After reading ur post I started to wonder if my fets had too much of a high rds why I was having so much heating . Would u recomend using these fets for this purpose. I await ur reply. Thank u

    • I’m not quite sure how would you use the sg3524 to create a sine-wave inverter, but I’m sure it’s possible. It’s impossible to tell if the Rdson of the fets you’re using is too low without knowing your current rating. Two things:
      - Are you driving the gate with a (PWM modulated) square wave, right?
      - If you’re using these FETs on the high-side, the drive stage is going to be challenging, you’ll probably need a boost circuit of sorts. You can read more about those here: http://www.modularcircuits.com/blog/articles/h-bridge-secrets/h-bridge_drivers/

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